EC8095 - VLSI DESIGN (Syllabus) 2017-regulation Anna University

EC8095 - VLSI DESIGN (Syllabus) 2017-regulation Anna University

EC8095	VLSI DESIGN	LPTC

3003

OBJECTIVES:

• Study the fundamentals of CMOS circuits and its characteristics.
• Learn the design and realization of combinational & sequential digital circuits.
• Architectural choices and performance tradeoffs involved in designing and realizing the circuits in CMOS technology are discussed
• Learn the different FPGA architectures and testability of VLSI circuits.

UNIT I	INTRODUCTION TO MOS TRANSISTOR	9

MOS Transistor, CMOS logic, Inverter, Pass Transistor, Transmission gate, Layout Design Rules, Gate Layouts, Stick Diagrams, Long-Channel I-V Charters tics, C-V Charters tics, Nonideal I-V Effects, DC Transfer characteristics, RC Delay Model, Elmore Delay, Linear Delay Model, Logical effort, Parasitic Delay, Delay in Logic Gate, Scaling.

UNIT II	COMBINATIONAL MOS LOGIC CIRCUITS	9

Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic, Dynamic Circuits, Pass Transistor Logic, Transmission Gates, Domino, Dual Rail Domino, CPL, DCVSPG, DPL, Circuit Pitfalls. Power: Dynamic Power, Static Power, Low Power Architecture.

UNIT III	SEQUENTIAL CIRCUIT DESIGN	9

Static latches and Registers, Dynamic latches and Registers, Pulse Registers, Sense Amplifier Based Register, Pipelining, Schmmit Trigger, Monostability Sequential Circuits, Astability Sequential Circuits. Timing Issues : Timing Classification Of Digital System, Synchronous Design.

UNIT IV	DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM	9

Arithmetic Building Blocks: Data Paths, Adders, Multipliers, Shifters, ALUs, power and speed tradeoffs, Case Study: Design as a tradeoff. Designing Memory and Array structures: Memory Architectures and Building Blocks, Memory Core, Memory Peripheral Circuitry.

UNIT V	IMPLEMENTATION STRATEGIES AND TESTING	9

FPGA Building Block Architectures, FPGA Interconnect Routing Procedures. Design for Testability: Ad Hoc Testing, Scan Design, BIST, IDDQ Testing, Design for Manufacturability, Boundary Scan.

TOTAL: 45 PERIODS

OUTCOMES: UPON COMPLETION OF THE COURSE, STUDENTS SHOULD ABILITY TO

• Realize the concepts of digital building blocks using MOS transistor.
• Design combinational MOS circuits and power strategies.
• Design and construct Sequential Circuits and Timing systems.
• Design arithmetic building blocks and memory subsystems.
• Apply and implement FPGA design flow and testing.

TEXT BOOKS:

1. Neil H.E. Weste, David Money Harris “CMOS VLSI Design: A Circuits and Systems Perspective”, 4th Edition, Pearson , 2017.(UNIT I,II,V)
2. Jan M. Rabaey ,Anantha Chandrakasan, Borivoje. Nikolic, ”Digital Integrated Circuits:A Design perspective”, Second Edition , Pearson , 2016.(UNIT III,IV)

REFERENCES:

1. M.J. Smith, “Application Specific Integrated Circuits”, Addisson Wesley, 1997
2. Sung-Mo kang, Yusuf leblebici, Chulwoo Kim “CMOS Digital Integrated Circuits:Analysis & Design”,4th edition McGraw Hill Education,2013
3. Wayne Wolf, “Modern VLSI Design: System On Chip”, Pearson Education, 2007
4. R.Jacob Baker, Harry W.LI., David E.Boyee, “CMOS Circuit Design, Layout and Simulation”, Prentice Hall of India 2005.