EI3352 Syllabus - Digital System Design And Applications - 2021 Regulation Anna University
EI3352 Syllabus - Digital System Design And Applications - 2021 Regulation Anna University
EI3352 | DIGITAL SYSTEM DESIGN AND APPLICATIONS | LTPC |
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2103
COURSE OBJECTIVES:
• To study various number systems and basic theorems of Boolean algebra
and gate level minimization and implementation..
• To outline the formal procedures for the analysis and design of combinational circuits.
• To analyze and design synchronous sequential circuits..
• To introduce the concept of asynchronous sequential circuits, PLCs and Logic Families..
• To introduce digital simulation techniques for development of application oriented logic circuit..
• To outline the formal procedures for the analysis and design of combinational circuits.
• To analyze and design synchronous sequential circuits..
• To introduce the concept of asynchronous sequential circuits, PLCs and Logic Families..
• To introduce digital simulation techniques for development of application oriented logic circuit..
UNIT I | BOOLEAN ALGEBRA AND GATE LEVEL MINIMIZATION (8+1 SKILL) | 9 |
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Review of number systems, types and conversion, binary codes, error
detection and correction codes (Parity and Hamming code). Boolean theorems
and properties – Boolean functions - Logic gates – Gate Level Minimization
using Karnaugh Map, SOP & POS simplification, Don’t Care conditions.
Implementations of Logic Functions using gates-NAND–NOR implementations.
UNIT II | COMBINATIONAL LOGIC (8+1 SKILL) | 9 |
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Design of adders, subtractors, Multiplexers - Combinational logic design using Multiplexers - Demultiplexers and their use in combinational logic design –2 bitMagnitude comparator, Code Converters - BCD to Binary and Binary to BCD, Encoder, Priority Encoder - Decimal to BCD, Octal to Binary, Decoders- BCD to Decimal and BCD to Seven Segment displaydecoder.
UNIT III | SYNCHRONOUS SEQUENTIAL LOGIC (8+1 SKILL) | 9 |
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Sequential logic - SR, JK, JKMS, D and T flip flops – characteristics and
excitation table - level triggering and edge triggering - counters -
asynchronous and synchronous type - Modulo counters - Shift registers -
design of synchronous sequential circuits – Moore and Mealy models- state
diagram; state reduction; state assignment.
UNIT IV | ASYNCHRONOUS SEQUENTIAL CIRCUITS, MEMORY AND LOGIC FAMILIES (8+1 SKILL) | 9 |
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Asynchronous sequential logic circuits - Transition and flow table - race
conditions, hazards & errors in digital circuits; analysis of asynchronous
sequential logic circuits. Memories: PROM, PLA – PAL, CPLD - FPGA. Digital
Logic gate realization and characteristics of TTL, ECL, CMOS families.
UNIT V | VHDL (8+1 SKILL) | 9 |
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RTL Design – combinational logic – Sequential circuit – Operators –
Introduction to Packages – Subprograms – Test bench. (Simulation /Tutorial
Examples: adders, counters, flip flops, Multiplexers & De
multiplexers).TOTAL 45 PERIODS
TOTAL 45 PERIODS
SKILL DEVELOPMENT ACTIVITIES (Group Seminar/Mini Project/Assignment/Content Preparation / Quiz/ Surprise Test / Solving GATE questions/ etc) | 5 PERIODS |
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1. Interpretation of Data Sheet of all logic gates.
2. Familiarization of any one relevant software tool (MATLAB/ SCILAB/ LABVIEW/ Proteus/ Equivalent open source software).
3. Design and verification of simple signal conditioning circuit thro simulation.
4. Realization of signal conditioning circuit in hardware.
5. Introduction to other advanced logic circuits not covered in the above syllabus circuits. (L5)
2. Familiarization of any one relevant software tool (MATLAB/ SCILAB/ LABVIEW/ Proteus/ Equivalent open source software).
3. Design and verification of simple signal conditioning circuit thro simulation.
4. Realization of signal conditioning circuit in hardware.
5. Introduction to other advanced logic circuits not covered in the above syllabus circuits. (L5)
COURSE OUTCOMES:: Upon completion of the course, students will be able
to
CO1 Convert various types of codes and number system & gate level
implementation of Boolean functions.(L2)
CO2 Apply K –Map for simplification and implementation of combinational logic circuit (L3)
CO3 Design the synchronous Sequential logic circuits namely counters, registers etc, (L5)
CO4 Analyze the asynchronous sequential circuits and explain the operation of memories and digital logic families (L4)
CO5 Design the VHDL coding for combinational logic and Sequential circuits. (L5)
CO2 Apply K –Map for simplification and implementation of combinational logic circuit (L3)
CO3 Design the synchronous Sequential logic circuits namely counters, registers etc, (L5)
CO4 Analyze the asynchronous sequential circuits and explain the operation of memories and digital logic families (L4)
CO5 Design the VHDL coding for combinational logic and Sequential circuits. (L5)
TEXT BOOKS:
1. M. Morris Mano, Michael D. Ciletti, “Digital Design: With an
Introduction to the Verilog HDL, VHDL, and System Verilog” Pearson India,
6th Edition, 2018.
2. Comer “Digital Logic & State Machine Design, Oxford,3rd Edition, 2016.
2. Comer “Digital Logic & State Machine Design, Oxford,3rd Edition, 2016.
REFERENCES:
1. D.P.Kothari, J.S.Dhillon “Digital Circuits and Design” Pearson
Education, 2016
2. Mandal,“DigitalElectronicsPrinciples & Application,McGrawHill,2013.
3. William Keitz, Digital Electronics-A Practical Approach with VHDL, Pearson,2013
4. Raj Kamal “Digital Systems – Principles and Design”Pearson Education India, 2012.
5. JamesW.Bignel,DigitalElectronics,Cengagelearning,5thEdition,2007.
2. Mandal,“DigitalElectronicsPrinciples & Application,McGrawHill,2013.
3. William Keitz, Digital Electronics-A Practical Approach with VHDL, Pearson,2013
4. Raj Kamal “Digital Systems – Principles and Design”Pearson Education India, 2012.
5. JamesW.Bignel,DigitalElectronics,Cengagelearning,5thEdition,2007.
List of Open Source Software/ Learning website:
1. https://nptel.ac.in/courses/117106114
2. https://nptel.ac.in/courses/117106086
3. https://nptel.ac.in/courses/106102181
4. https://archive.nptel.ac.in/courses/108/105/108105132/
2. https://nptel.ac.in/courses/117106086
3. https://nptel.ac.in/courses/106102181
4. https://archive.nptel.ac.in/courses/108/105/108105132/
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